Name: Verification Expert Help (Get help right now) - Codementor
Brand: Codementor
Rating: 3 (51 reviews)

Verification

Get help from vetted Verification experts

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Armen

US$50 / 15 mins

SystemVerilog, UVM expert

- Incentive experience of architecting and implementing OVM/UVM SystemVerilog verification environments for digital design verification - Developing verification components, se...

VerificationVerilog UVM SystemVerilog

Sabine Schmaltz

US$25 / 15 mins

Senior Full-stack developer who likes Svelte and typed languages

I've been dabbling in technology since I was a kid, and later went on to get a PhD in Computer Science. After leaving academia, I learned a lot about web development - from Python/...

VerificationComputer Science Rust Svelte TypeScript OCaml Node.js Django Elasticsearch JavaScriptFormal VerificationApache cordova Web Development Elm SQL Express.js Isomorphic javascript Server side rendering Promises Functional Programming Django forms Python Django allauth Mobile friendlyHigher order logicIsabelle/HOLIsomorphic webapps Django templatetags Query language Django orm Mobile first Django templates Responsive Layout jQuery UI jQuery HTML5 HTML AndroidStandard MLStyletronDomvm

Muhammad Rafique

US$5 / 15 mins

I have several years of experience in Software Automation, Software Quality Assurance, Testing, Analysis, Big Data/Business Intelligence(BI)/Data Warehouse(DW) Analysis, Consultanc...

Gaurav Bansal

US$15 / 15 mins4.9 (9 reviews)

Lead Backend Developer with 8+ yrs of experience (Working at VISA Inc)

Working as Staff Software Engineer at VISA INC. Skilled in Java, Microservices, Data Structures, Spring Boot, Rest Apis, MVC, CICD, Bamboo, Jenkins, OOPS, Angular, TypeScript, Java...

Sameh ElAshry

US$15 / 15 mins5.0 (39 reviews)

Verification Verilog && VHDL && UVM & SystemVerilog Expert

Sameh El-Ashry is working as senior digital verification engineer with 6+ years of industry experience. His work involves the verification of digital wireless communication IPs inc...

UVM SystemVerilog Verilog VHDL (VHSIC Hardware Description Language)FPGA C programming Python Tools ShellVerdiQuestasim Version control Makefile Perl

Within 15 min, I was online with a seasoned engineer who was editing my code and pointing out my errors … this was the first time I’ve ever experienced the potential of the Internet to transform learning.

Tomasz Tunguz

Venture capitalist at
Redpoint Ventures

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