Dinyo Ivanov

Developing test bench architecture. Implementation of UVM approach with Analog-Mix signal simulations. UVC creation. Methodology development.

Define and track detailed test plans for the different modules and top levels Implement scalable test benches including checkers, reference models, and coverage groups in SystemVerilog Keep track of coverage metrics and bugs encountered Implement self-testing directed and random tests Develop the scripts and code necessary for the proper automation Lead debugging and runtime optimization efforts Support post silicon bring up and debug activities Taking active part in the analysis and negotiations of customer requirements

Participating in the verification processes of L2/L3 Network Switching and routing ASICs and various subsystems within these chips Understanding the architecture and implementation of these chips and coming up with in depth test plans for verifying various key networking features such as L2/L3 traffic streaming, traffic management, scheduling and shaping of traffic, latency and performance characterization of chips and systems. Developing verification environments including testbenches and verification API’s associated with the chip architecture to enable testing of various features within the chips as well as scripts and Makefiles as required to run the environment in various tool chains. Implementing test plans into executable test suites using a cutting edge Systemverilog verification environment as well as leveraging high performance verification platforms such as testbench acceleration and Incircuit emulation as required. Executing the verification process to completion in presilicon using various functional and code coverage metrics as measures of completion