Armen

Incentive experience of architecting and implementing OVM/UVM SystemVerilog verification environments for digital design verification

Developing verification components, setting up regression systems with latest EDA tools.

Experience with an industry available Cadence Palladium emulator

Understanding of end-to-end digital design verification processes, overall verification strategy and methodology from test plan creation, through to verification closure.

Fluent in verification languages: SystemVerilog, Python, TCL

Verification methodologies: OVM, UVM