Jason Pennington

Jason Pennington

Mentor
5.0
(11 reviews)
US$25.00
For every 15 mins
61
Sessions/Jobs
ABOUT ME
Senior FPGA Engineer with 10+ years experience
Senior FPGA Engineer with 10+ years experience

My area of expertise is signal processing, first in MATLAB or Python to characterize the algorithm. Then the fun part is to implement the algorithm on an embedded platform. FPGAs and VHDL are my favorite platform right now.

I also join tinkering at home with my Raspberry PI.

Eastern Time (US & Canada) (-04:00)
Joined July 2019
EXPERTISE
10 years experience | 1 endorsement
I've worked in 4G and 5G communications, including Multiple-Input Multiple-Output communications which 4G and 5G are built on. I mostly w...
I've worked in 4G and 5G communications, including Multiple-Input Multiple-Output communications which 4G and 5G are built on. I mostly work in the physical layer so schemes like Orthogonal Frequency Division Multiplexing and the other variants such as OFDMA and SC-FDMA. With these technologies there are some smaller building blocks that I am well versed in such as frequency mixing and filtering. Some slightly more advanced concepts like autocorrelation and correlation. I have experience with QR decomposition and LU decomposition.
7 years experience | 2 endorsements
I have designed from scratch many systems that include signal processing on an FPGA. The most interesting is a recent technology from Xil...
I have designed from scratch many systems that include signal processing on an FPGA. The most interesting is a recent technology from Xilinx in which the ADCs and DACs are on the same silicon as the FPGA and an ARM processing. This platform is known as the RFSoC. I have experience on mostly Xilinx FPGAs but I have used Altera FPGAs in the past. In 2015 I taught a course that used an Altera FPGA in which we covered the basics of VHDL programming. I have experience in developing SPI controllers for off-chip communication as well as DDR Controller to save off a lot of data for future use.
XilinxAlteraQuestasim rfsoc
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5 years experience
Most of my experience in Python is to test my VHDL code. I use an automated methodology to generate stimulus and compare results. This ty...
Most of my experience in Python is to test my VHDL code. I use an automated methodology to generate stimulus and compare results. This type of programming is more scripting experience than true object-oriented programming. I have developed some small games in Python. These games are used for teaching high school students the fundamentals of personal finance.

REVIEWS FROM CLIENTS

5.0
(11 reviews)
Rowen Simpson
Rowen Simpson
January 2022
Jason reviewed my VHDL and gave some detailed feedback on potential areas of improvement followed up by suggestions on a path forward
D Smith
D Smith
June 2021
Great help, fast and efficient.
Mark
Mark
April 2021
Jason is extremely educated on the topic of signals and MATLAB. If I have any questions in the future, I will definitely reach back out to him. Thanks for the help!
Fatima
Fatima
June 2020
Jason provides regular updates about the progress and detailed explanation of raised questions. He finished before the deadline and didn't hesitate to help with other matters, which helped me to understand some basics of VHDL better.
Saul Iversen
Saul Iversen
June 2020
My first session with Jason. He is polite, articulate, and knowledgeable.
Fatima
Fatima
June 2020
Jason is a great mentor, and knowledgable, he simplified concepts for me and spent considerable time answering my questions. Would definitely get back to him if I've ever needed help with VHDL.
Prathosh
Prathosh
June 2020
Jason is a patient, intervening, and a vastly knowledgeable person. I can’t thank him enough for all the help that he give me, with his help I was able to take my work to the next level. I will definitely recommend him as a tutor.!
Removed User
Removed User
June 2020
Super fast and gentle! The review was very clear and helpful. Solved all of my problems!
Jack Fuhrer
Jack Fuhrer
May 2020
Jason was very helpful and insightful in troubleshooting my problem, Jason took his time to explain and ensure i understood the problem as well as provided the solution too. Very helpful and great guy
SOCIAL PRESENCE
EMPLOYMENTS
Senior Engineer
Defense Engineering Corp
2020-01-01-Present
I work as a lead FPGA design engineer.
I work as a lead FPGA design engineer.
VHDL (VHSIC Hardware Description Language)
VHDL (VHSIC Hardware Description Language)
Principal FPGA Engineer
Northrop Grumman
2016-10-01-2019-12-01
Lead FPGA design engineer. Signal processing and interfacing with DDR and other peripherals.
Lead FPGA design engineer. Signal processing and interfacing with DDR and other peripherals.
Signal Processing
VHDL (VHSIC Hardware Description Language)
Signal Processing
VHDL (VHSIC Hardware Description Language)
PROJECTS
FPGA and SBC BookView Project
2019
I wrote a small book available for free with some tips for getting started in two popular embedded processing platforms. The single board...
I wrote a small book available for free with some tips for getting started in two popular embedded processing platforms. The single board computer (SBC) and the Field Programmable Gate Array (FPGA). Both of these platforms can be difficult to get started in because they can feel a little bit intimidating. This books aims to help alleviate some of that anxiety by breaking the problem down into small manageable chunks that can be learned and understood. I also encourage feedback on the book for ways it can be made better.
VHDL (VHSIC Hardware Description Language)
Python 3
Julia
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VHDL (VHSIC Hardware Description Language)
Python 3
Julia
C programming
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