Vincent Toomey

June ‘23 – Present: GeoSensors– Self Employed Contractor

• Field Programmable Gate Array (FPGA) Emulation Engineer with a Toronto based company.
• Working predominantly on FPGA RTL to replace their existing vendor constrained solution with a fully customised, parametrisable equivalent.

Key Achievements

• Defined the architecture, specification and implementation of a custom RTL DSP pipeline consisting of an analog front end, hardware efficient FIR Filters and data handlers with self clearing IRQs.
• Developed a hybrid SystemVerilog/UVM environment to test this pipeline in ModelSim.
• Created an FPGA environment allowing all parts of the compilation to be implemented to multiple targets thus eliminating the previous vendor specific constraints.
• Developed a design enablement environment along with various scripts generating RTL and testbench test patterns.

April ‘21 – June ‘23: Synopsys – Staff IC Design Engineer

• Digital IC design engineer with the PCIe IP Development team.
• Experience in the design of industry standard configurable IP, deliverable to multiple clients.
• Working predominantly on custom RTL design on the PCIe Transmitter.

Key Achievements

• Successfully completed the design of a front-end Application module allowing easy connectivity between a users application interface and the PCIe Transaction Layer.
• Worked extensively on the standardisation of various PCIe specification related types and functions for use across the PCIe stack with an emphasis on improved speed to market as well as design robustness.

April ‘16 – April ‘21: Intel - Senior IC Design Engineer

• Digital IC design engineer with the IWG/Movidius VPU IP Group at Intel Leixlip.
• Experience in the design of ISP hardware accelerators.
• Experience in the design of power delivery control logic for an ultra-low power wearable SoC.
• Working predominantly on custom RTL design, SoC integration, hardware validation and design enablement tools and flows.

Key Achievements

• Successfully completed the design of a HDR (High Dynamic Range) tone-map hardware accelerator for the successor to the MyriadX SoC. This block of IP was defined by the ISP algorithm team and was transposed to both an RTL and C++ model implementation. This HDR IP was a key component of the next generation ISP.
• Additional design work on common re-usable IP, instantiated in both ISP and external designs. This included items such a programmable s-curve function, descriptor load logic and hardware dividers.
• Significant validation work on both the RTL and C++ model implementations of several ISP filters.
• Design enablement support with respect to tools (RTL generation) and methodologies (memory generation).
• Performed Spyglass CDC analysis on the SoC Fabric crossing to the ISP pipelines.
• Successfully completed the design of a power management unit (PMU) for an ultra-low power wearable SoC. This block of IP was defined with both the SoC and platform hardware architects and controlled the power delivery IPs and SoC power domains. This was implemented with a goal towards minimal power consumption in a deep sleep state to maximise battery longevity. This SoC was a key component of the VAUNT Intel Glasses.
• Carried on this work in implementing a programmable version of the above PMU for use in future SoCs.