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Srinivasan Venkataramanan

Srinivasan Venkataramanan

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Rising Codementor
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ABOUT ME
SystemVerilog, UVM, Low power expert (Intel/Philips/Synopsys)
SystemVerilog, UVM, Low power expert (Intel/Philips/Synopsys)

Seasoned VLSI engineer with 23+ years of experience. Have been involved in functional design and verification of more than 25 chips so far. My areas of interest are advanced verification solutions and methodologies such as SystemVerilog, UVM, OVM, VMM, Assertion-Based Verification, formal verification, etc. I have also demonstrated leadership in key areas such as Low Power verification using UPF (IEEE 1801), Specman based verification (IEEE 1647).

Co-authored the following books:

  • Unleashing UVM - Just Do It!
  • SystemVerilog Assertions Handbook
  • A Pragmatic Approach to VMM Adoption
  • Using PSL/Sugar, 2nd Edition

Trained more than 15,000 engineers across the globe on SystemVerilog, UVM, UPF, and more. Served as Vice-Chair in eWG (IEEE 1647 e-language Working Group). Have been a regular presenter at various world-wide conferences such as DVCon (US, India, Europe), DAC, SNUG, etc. Also served in various capacities in technical committees of DVCon (US, IN, China), DAC.

London (+01:00)
Joined July 2020
EXPERTISE
SystemVerilog
15 years experience
UPF
5 years experience
UVM
11 years experience

REVIEWS FROM CLIENTS

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SOCIAL PRESENCE
GitHub
rtgen_2019
0
0
vunit_icarus
VUnit on free Icarus Verilog simulator
SystemVerilog
0
0
PROJECTS
PySlint - a SystemVerilog testbench Linter, review toolView Project
2023
SystemVerilog is a vast languages with many subtle coding tricks especially in the testbench part of it. PySlint is an opensource, Python...
SystemVerilog is a vast languages with many subtle coding tricks especially in the testbench part of it. PySlint is an opensource, Python based testbench linter!
Verilog
SystemVerilog
Python 3
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Verilog
SystemVerilog
Python 3
UVM
SystemVerilog Assertions
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